1. Field of the Invention
This invention relates to a semiconductor device including a semiconductor thin film and a method of manufacturing the semiconductor device.
2. Description of the Related Art
FIGS. 31A, 31B and 31C illustrate the structure of a semiconductor device having a gate all around (GAA) type of thin film transistor, such as described on page 595 of IEDM'90 (International Electron Devices Meeting) Technical Digest, and showing a method of manufacturing this transistor. On a silicon substrate 1 shown in FIGS. 31A to 31C are formed a first silicon oxide film 2, which is an insulating film provided as a base for formation of electrodes of the transistor, and a channel silicon film 3 formed of a silicon monocrystal for forming output electrodes of the transistor. The silicon substrate 1, the first silicon oxide film 2 and the channel silicon film 3 are formed by a manufacturing method called SIMOX (Separation by IMplanted OXygen). In a SIMOX process, oxygen is introduced into the silicon substrate 1 by high-concentration ion implantation to form an oxide film, thereby separating the silicon substrate 1 and the channel silicon film 3.
An opening (hole) 4 is formed in the first silicon oxide film 2 to enable the gate electrode 6 to cover a portion of the channel silicon film 3 from above and below as viewed in the illustration (in the direction of arrows q and q' shown in FIG. 31B) in a sandwiching manner. Such formation of the gate electrode 6 characterizes this GAA transistor. A second silicon oxide film 5 is formed as a gate insulation film for insulation between the channel silicon film 3 and the gate electrode 6. The gate electrode 6 is a polysilicon film.
FIGS. 32A through 32E are diagrams of a process of manufacturing this semiconductor device. Each of these figures is a cross-sectional view taken along a line corresponding to the line 32--32 of FIG. 31C; FIGS. 32B, 32C, and 32E are cross-sectional views of FIGS. 31A, 31B, and 31C, respectively.
FIG. 33 is a cross-sectional view taken along the line 33--33 of FIG. 31C.
The GAA transistor, having such a structure, is characterized in that a large current flows through it when it is on. In the GAA transistor, as shown in FIGS. 31C, 32E and 33, the gate electrode 6 is formed in such a manner that the channel silicon film 3 is sandwiched between portions of the gate electrodes 6 facing the two surfaces of the channel silicon film 3 from above and below (in the directions q and q' indicated in FIGS. 31B and 32E). A channel is formed in the channel silicon film 3 in response to a bias voltage applied to the gate electrode 6 to affect a current flow. In the structure shown in FIGS. 31C, 32E and 33, therefore, the channel is formed both at the upper and lower interfaces on the channel silicon film 3 opposite to the directions q and q'. Accordingly, the current flowing through the transistor when the transistor is on is at least twice that in the conventional transistor having a gate electrode only formed on one side. Moreover, if the channel silicon film 3 is thin, the channel is formed throughout the channel silicon film so that a larger current can flow therethrough.
The method of manufacturing the GAA transistor will next be described. First, a surface silicon film 21 of a SIMOX wafer is selectively etched to form a desired pattern (FIG. 32A), and channel silicon film 3 is formed in accordance with the desired pattern by photolithography (FIGS. 31A, 32B). Next, a portion of first silicon oxide film 2 located below a portion of the channel silicon film 3 of the GAA transistor in which a channel is to be formed is removed by wet etching to form opening 4. As a result, the portion of the channel silicon film 3 in which a channel will be formed extends like a bridge over the opening 4, as viewed in the cross-sectional views of FIGS. 31B and 32C.
Next, second silicon oxide film 5 to be used as a gate insulation film of the transistor is formed (FIG. 32D). Second silicon oxide film 5 covers all surfaces of the channel silicon film 3, because it is formed by chemical vapor deposition (CVD). Thereafter, a polysilicon film for forming gate electrode 6 is formed by deposition on the second silicon oxide film 5 and is patterned in accordance with a predetermined pattern by photolithography. In this manner, the GAA transistor is completed with the gate electrode 6 on formed on both the upper and lower sides of channel silicon film 3 in which a channel is formed (FIGS. 31C, 32E). A channel is formed on each of the upper and lower sides of the channel silicon film 3.
As seen in FIG. 33, a cross-sectional view of the thus-formed GAA transistor, a gate electrode portion 6b formed below the channel silicon film 3 remains without being etched at the time of patterning, since the gate electrode 6 is etched from above. The gate electrode 6b is therefore longer than a gate electrode portion 6a formed above the channel silicon film 3.
These conventional semiconductor devices have been constructed and manufactured by a SIMOX process. This is because channel silicon film 3 is formed as monocrystal in order that a larger current can flow through the channel. However, it is not possible to form a silicon monocrystal by superposing it on the GAA transistor formed in this manner. The GAA transistor can be formed in a structure of at most one layer and not in a multilayer structure. It is therefore difficult to increase the integration density of the conventional GAA transistors.
In the conventional semiconductor device manufacturing process, channel silicon film 3 is first formed from monocrystal silicon film 21, and opening 4 for forming a thin film transistor is thereafter formed. Therefore, dry etching cannot be performed for forming opening 4 (because it is difficult to remove the portion of the first silicon oxide film 2 hidden by the channel silicon film 3), and wet etching using a liquid such as hydrofluoric acid. Wet etching, however, is isotropic etching, whereby a material is etched equally in all directions. Accordingly, the first silicon oxide film 2 is etched not only in the direction of the silicon substrate 1 (in the direction q in FIG. 32C) but also in a direction parallel to the silicon substrate, e.g., a direction p perpendicular to the direction q, as shown in FIG. 32C, so that the resulting opening 4 is slightly larger than the resist film pattern provided in the lithography step in the direction p. It is therefore difficult to form opening 4 in accordance with a very fine pattern for an increase in the integration density of GAA transistors.